Over the last four decades, the semiconductor industry has continually improved the speed and power of integrated chips (ICs) by reducing the size of components within the ICs. In large part, the ability to shrink the size of components within an integrated chip is driven by lithographic resolution. In recent years however, tool vendors have been unable to decrease the wavelength of illumination sources (e.g., to successfully implement EUV or x-ray lithography), so that developing technology nodes often have minimum feature sizes less than the wavelength of illumination used in exposure tools. Therefore, IC fabrication processes have been forced to use tricks (e.g., immersion lithography, dual tone resist, etc.) that improve the resolution of existing lithography tools in a manner that extends their usefulness.
Double patterning lithography (DPL) is one lithography strategy that is used in advanced technology nodes. To perform DPL, an IC layout is decomposed according to an algorithm that assigns different colors (e.g., black and gray) to shapes separated by a space less than a printable threshold. The different colors correspond to different photomasks, such that features of a same color are formed on one mask of a double patterning exposure. By separating IC layout data onto different masks, printing below a printable threshold is enabled since the features comprised within each separate mask do not violate the printable threshold.